The present invention relates generally to data communication, and more particularly to data communication in a local area network.
It has long been a common practice to interconnect a plurality of digital computers or data processors (CPUs) via a cable in a network so that data can be transferred between the processors in the network. Networks of this type, generally known as local area networks (LANs), may include a token-passing network in which a token is transferred or passed between processors to allow only that processor which then has possession of the token to transmit data to a designated other processor in the network so long as the transmitting processor retains the token.
Each processor in the network includes a local area network (LAN) controller, which is connected, typically through a LAN driver, to the cable by which the processor is interconnected with the other processors in the network. Also, typically associated with each processor in the network is a buffer memory, typically a random-access memory (RAM), which temporarily stores data either received, via the controller, from an external processor to be subsequently transferred into the processor's main memory, or data from the processor that is to be transmitted along the cable to an external processor also via the network controller.
The buffer memory is thus shared by the processor and its local area network controller. In order to transmit data from one processor to another processor along the network, the data from the transmitting processor is first loaded into its resident buffer memory. The LAN controller associated with the transmitting processor then reads the data thus stored in the buffer memory and transmits that data on the cable to a designated receiving processor. The LAN controller associated with the receiving processor receives this transmitted data and then loads that data into its own resident buffer memory from which the transmitted data is then read into the main memory of the receiving processor.
Since access by the LAN controller and the processor to the buffer memory are asynchronous, some form of arbitration scheme is generally provided to control access to the buffer memory between the associated processor and LAN controller so as to prevent access contention to the buffer memory.
For this purpose, the LAN controller typically includes an arbitration circuit, which, through the generation of appropriate timing signals, allocates access to the buffer memory between data being received from or transmitted to an external processor, via the LAN controller, and data either received from or being sent to its local processor via the PC bus. A typical LAN controller that includes such an arbitration circuit is the COM90C65 made and sold by Standard Microsystems Corp. of Hauppauge, N.Y.
In the conventional arbitration circuit, such as that included in the COM90C65 LAN controller, allocation of access to the buffer memory between the processor and the LAN controller is assigned to that unit which first requests access to the memory. That is, if access to the buffer memory is requested by the processor prior to the LAN controller, the latter must wait until the request from the processor has been completed. Conversely, if the LAN controller requests access to the buffer memory before the processor, the processor must wait for access to the buffer memory pending the completion of data transmission by the LAN controller to or from the buffer memory. On those rare occasions when both the processor and LAN controller simultaneously request access to the memory, the processor is given priority over the LAN controller to the buffer memory.
In the past, when processors and buffer memories operated at relatively low speeds, placing the processor into a wait state while the buffer memory serviced a request from a LAN controller had only minimal and consequently acceptable adverse impact on overall network performance. However, as the operating speeds of memories and processors have increased in recent years, this method of arbitration has become increasingly disadvantageous since it tends to decrease overall network throughput in those faster systems by forcing the processor to remain in a wait state for access to the resident buffer memory until a LAN controller request to the buffer memory is completed. In the higher-speed networks, access for an uncontested read of the buffer memory is typically 400 ns as compared to an access period of 1400 ns for a processor required to read from the buffer memory when the processor is forced to wait for the completion of a LAN controller access to the memory.
In one attempt to improve network throughput and operating speed, the buffer memory has been implemented as an external dual port static RAM. In this scheme, the processor directly accesses one port of the buffer memory rather than use the arbitration circuit within the LAN controller, while the LAN controller accesses the second port of the buffer memory by using the arbitration circuit. Although this scheme improves throughput and eliminates memory contention, the cost of dual port static RAMS is higher than that of conventional single-port static RAMS so that this design is not cost effective. To reduce the cost of implementing this scheme, a dual port static RAM along with the LAN controller could be fabricated on a single integrated circuit. However, the amount of circuitry and silicon needed to implement the dual port static RAM in this manner would far exceed that of a conventional static RAM combined with the arbitration circuit since a dual port static RAM requires twice the number of bit lines, word lines, select devices and sense amplifiers than required for a conventional static RAM. This approach to achieving increased operating speed is thus also not practical.
It is accordingly an object of the present invention to provide an improved LAN controller arbitration scheme in which system throughput and increased operating speed are achieved.
It is a further object of the present invention to provide an arbitration scheme in a LAN controller that more efficiently arbitrates access to and from a shared buffer memory.
It is another object of the present invention to provide an improved arbitration scheme of the type described without the need for a more costly and more complex dual port static RAM.
It is a general object of the present invention to provide a more efficient arbitration scheme for use in a LAN controller which is cost effective and practical.
It is still a further object of the present invention to provide an arbitration circuit for use with a LAN controller and buffer memory which speeds up loading or reading from the memory by the processor.